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I successfully applied ISD4004 and AT89C51 microcontroller design of the station signal automatic voice broadcast system, the railway line through the station the uplink and downlink control, vehicle scheduling, main and auxiliary power system to enable other multi-channel signal detection and acquisition, according to security risks prevention requirements, security warning from the SCM check voice messages and broadcast, to achieve prompt and safe operation of the alarm. System console room at the station signal installation, stable operation, the signal broadcast accurate, and achieved good results.
1 hardware design
system hardware design block diagram shown in Figure 1 by the microcontroller AT89C51, ISD4004 voice circuits, audio power amplifier circuit, a programmable parallel interface 8255 , optical isolation, level shifting, signal input interface, the system clock, reset and keyboard unit circuit.

1.1ISD4004 features
ISD4004 series voice storage chip using CMOS technology, contains the oscillator, anti-aliasing filter, smoothing filter, audio amplifier, automatic squelch, and high-density multi-level flash store display, built-in microcontroller serial communication interface. Chip micro-controller, all operations must be controlled, the operation command via the serial communication interface (SPI or Microwire) give as gifts. External audio signals in the chip-level multi-volume direct analog storage technology, information can be multi-stage process, each sample value directly stored in the flash memory chip, so can be very real, natural reproduction of voice, music , tone and effect sound. Stored in the flash memory chip of information that can be saved in case of power failure 100 years. Chip operating voltage of 3V, operating current 25 ~ 30mA, maintain current 1μA, no power, single recording time 8 ~ 16min, recording can be repeated 100,000 times.
1.2ISD4004 pin and package
ISD4004 28-pin SOIC package, the pinout shown in Figure 2.

1.3ISD4004 with AT89C51 microcontroller interface
ISD4004 SPI serial interface to operate in accordance with the SPI synchronous serial data transmission protocol, all single-chip serial data transmission begins with the master sent to the ISD4004 falling edge of chip select signal SS. SS must remain in the low transmission period, between the two remains high command. Serial data input from the MOSI pin of the serial synchronous clock rising edge is latched to the ISD4004 MISO pin serial data output of data out of the falling edge of SCLK. ISD4004 any of the recording and playback operations (including fast-forward), are carried out by sub-addresses, each containing a number of lines, each line is equivalent to the storage unit, the row address clock signal RAC under the control of recording information storage management. RAC signal cycle is 200ms, high duty cycle is 3 / 4. When the recording and playback operation to the end of the address within the memory cell, the EOM or OVF will generate a flag signal the end, if you encounter EOM or OVF, then generate an active-low INT interrupt signal, the interrupt status in the next SPI beginning of the cycle to be cleared. ISD4004 to connect with AT89C51 microcontroller shown in Figure 3.

ISD4004 chip-select signal SS pin and the AT89C51 microcontroller I / O port P1.0 connected by the program instructions to produce effective low-level signals. Serial data input pin MOSI and MISO serial data output pin with P1.1 and P1.3 are connected to the serial data send and receive information under the control of program instructions from the on-chip shift register latches, the synchronous clock signal SCLK from the MCU P1.2 control. RAC and the row address clock interrupt request signal INT, respectively P3.2 (INT1) and P3.3 (INTO) connection.
1.4 audio output
system signal corresponding to the voice prompts, such as “train came up, the range of occupation,” “upward departure request, signal open” and other information, by Address by special equipment has been cured to the ISD4004 segment storage unit within the E2PROM. Under program control, the corresponding voice signal from the ISD4004 13 feet (AUOUT) output, the coupling capacitor C4 and the volume control potentiometer RW, into low-noise power amplifier integrated circuits for amplification, to promote the speaker sound. To output audio noise to a minimum, the system of separate analog and digital ground traces, as close to the power supply is connected at the end, and were diverted to the ISD4004 chip VSSA and VSSD pins, decoupling capacitors should be as close as possible chip.
1.5I / O port expansion
system 36 signals to be handled by the microcontroller, at least 36 I / O port lines to meet demand, by remaining AT89C51 The I / O port is clearly not enough, the need for I / O port expansion. System uses programmable parallel input and output interface chip shortage of 8255 expansion I / O port, hardware-specific connection in Figure 4. 8255 is a microprocessor system with the standard expansion of the external parallel interface circuit using NMOS process, the 40 foot double row DIP DIP package. 8255 exchange information with external devices through port A, B port, c port 24 I / O lines to complete, each port is 8. Where C is divided into the port, Port C (PC7 ~ PC4 high four) and the next port C (PC3 ~ PC0 low 4). The method can be programmed to specify the input port of the work, the master program initialization to complete. 8255 P1.4 completed by the selection signal, address bus A0 and A1 through the address latch 74LS373 lock.

1.6 signal conversion
system signal from the station control room signal relay contacts, the main switch is AC 24V signal must be converted to single-chip system can match the TTL level, that is, transform the AC to DC 5V 24V , the signal level conversion circuit shown in Figure 5. AC signal from the rectifier diode D32, capacitor C32 filter, the input current limiting resistor R32 optocoupler 4N25, by the internal LED and light sensitive photoelectric conversion receiver to achieve effective control, while the electrical network and an external signal single-chip control system to isolate, improve system reliability and performance. Transform the output signal is low, in order to maintain the input signal and output signal level synchronization, plus after-class inverter, the output standard TTL5V signal sent to the parallel interface 8255.

2 overall design software

system software design directly affects the overall system performance. Software main function is real-time access to the railway signals, signals accurately determine the validity and reliability to find the signal corresponding to the voice storage address, remove the information in real-time broadcast. Software programs, including master program, the signal check program, voice broadcast, data transmission program, ISD4004 of power and power-down procedures. Program several times using delay subroutine, because the structure is simple, versatile, this will not elaborate.
2.1
master program master program flow shown in Figure 6, the system is initialized on power to complete the I / O port, the signal unit and signal flags bit cleared and the initial set ISD4004 and 8255, and completed when the system power-on self-test and product information voice broadcast advertising. Then check the incoming signal and voice broadcast cycle control processes. In order to prevent the system from false alarms, omissions, or even reported in the program designed to ensure that factors, such as image stabilization to determine the use of signal delay, signal level to determine the level of cross signs and signals unit address look-up table and other methods to improve system reliability.
2.2 signal check signal
subroutine subroutine processes the query shown in Figure 7, the system occupied more than 30 signals were part of AT89C51 microcontroller I / O lines and programmable interface 8255 A, B, C port input line 24. Program for multi-channel signals each query, and the arrival of the effective signal storage sub-unit mark, to pass parameters to the master program.

2.3 voice broadcast subroutine
ISD4004 chip micro-controller, all operations must be controlled by the operation command through the interface into the SPI serial communication protocol. SPI control register controls the chip sound recording, information retrieval, power, power-down, start and stop functions, from software programming instructions to change the SPI control register control bits, SPI control register control bits shown in Figure 8, command format is: 8-bit control code 16-bit address code. ISD of any operation set in the run position C4 starts, set 0 end, if you encounter EOM or OVF, an interrupt is generated, using the “read” instruction to interrupt the state of the MISO pin displacement of ISD, the control and address data synchronization from the side into MOSI. So pay attention to whether the data into the ongoing operation of the device compatibility. Of course, allows one SPI cycle, while the read status and start a new operation (the new data into the device may not be compatible with the current operation).

voice broadcast subroutine in strict accordance with the requirements of the above programming ISD4004, the process shown in Figure 9. System recognizes the current broadcast signal is available through the store to find the voice address to get 16-bit broadcast address. First call on the electronic program, to send power commands, then wait for a delay of about 25μs, and then transfer 16-bit playback and 8-bit start address parameter start playback from the specified address of the instruction, data transmission subroutine calls respectively to complete the information the broadcast.

2.4 data transmission subroutine
data transmission subroutine flow chart shown in Figure 1O, mainly 16-bit address and 8-bit playback function control command data in accordance with the standard SPI protocol, the serial clock synchronous transmission of the ISD4004 of MOSI.
2.5 power, out of electronic program
ISD4004 can realize the power management mode of operation, through the programming instructions to complete power and power-down operation, the program flow chart shown in Figure 11 and 12. The chip into low-power state after power-down, about 1μA current consumption, power-on operation is completed only after the chip to work properly.

3 Conclusion
described ISD4004 chip design based on single-chip control signal voice broadcast system station control room in a practical application examples, describes the system hardware and software design, its purpose is to provide a multi-line voice prompts industrial process control or alarm computer control module, can be slightly modified and easily with conventional industrial control systems or equipment used in conjunction with, even with complex systems can be easily used in conjunction with the DCS system and, complete a variety of industrial control and monitoring alarm system working state and operating tips.

Abstract: The long-range temperature control of the composition and working principle, design of FPGA-based digital remote temperature control system data acquisition and control systems, using Altera FPGA implementation Cyclonell series, including data collection, data communication and other control functions, focusing on the hardware and software implementations. The CNC system has high accuracy, low power consumption. Keywords: remote temperature; FPGA; data acquisition and control system; Nios Ⅱ
0 Introduction
research in some special places and industrial production units, for a variety of conditions, the instrument is often not close to the actual measurement of body temperature; while some of the sensors used in the past when using the various environmental factors, making the sensor measured the temperature does not accurately reflect the temperature of the measured object. Therefore, people need to find a long-range temperature control, can accurately measure the temperature of the object, and real-time monitoring of temperature data.
remote temperature measurement device is a passive temperature sensors can be used for remote detection temperature of the object, in scientific research and industrial production has played an important role. Because when people use the device temperature measurement range, sensitivity, demanding, and because the design of today remote sensing instruments become more and more low-power high-density and miniaturization, therefore, require temperature control device for data processing and system with high reliability, high-resolution, real-time, small size and other characteristics. As a powerful FPGA logic speed, you can use a variety of interface level communication with the outside world, you can easily update the program in order to achieve a variety of functions, so this use Altera Cyclone Ⅱ series of FPGA Core long-range temperature control CNC system design, implementation of the system functionality and miniaturization.
1 remote temperature control system architecture block diagram shown in Figure 1. By the infrared probe, the photoelectric conversion unit, amplifier, data acquisition and data processing circuits and control systems and other functional modules. Infrared probe for collecting objects emit infrared light, the useful signal for transmission to the distant and the people where the action is, the last use of data processing and control system to control.

data processing and control system receiving computer instructions transmitted to control system operation. After a system power, infrared light receiving antenna to receive analog signals through long-distance transmission, the signal amplified through an A / D conversion and then sent to data processing and control system, the data processing and control system for data collection and storage, and computer data communications, work status control. Data processing and control system in the long-range temperature control in an important position. Data acquisition, data processing and control system and its peripheral circuit by FPGA circuits, data acquisition system, the level conversion circuit, the bus interface circuit and other components shown in Figure 2.

FPGA according to the system itself timing and control commands into the computer, data acquisition control circuit for data collection. At the same time, FPGA internal configurable soft-core Nios Ⅱ processing computer system will provide the calibration values ??to correct front-end analog circuits caused by the deviation of the actual error is small and thus generate the curve equation. After calibration, the system can be easily separated from the computer for remote temperature measurements, the temperature of objects can be used for on-line real-time detection, a large number of collected data to a computer for analysis. CNC system using Altera Cyclone Ⅱ series of EP2C8 FPGA core design. Cyclone Ⅱ devices using 90nm, low-K dielectric process values ??by minimizing the silicon area, on a single chip can support complex digital systems. Many user-defined I / O pins for external help system expansion. Its configuration PROM using Altera offer 16MB of EPCS4 serial configuration PROM, with the configuration device in-system programming (ISP) capabilities and multiple programming capabilities, including ISP and FLASH memory with the access interface and other features. Data acquisition circuit AD ADC AD7675, the chips work only needs to provide 5 V power supply and typically consumes 15mW, chip to speed 100KSPS, selectable parallel or serial sample data output, external optional 5 V or 3.3 V interface levels. Measured analog input voltage range of -2.5 ~ 2.5 V, can be done without losing the maximum 16-bit code.
2 hardware design
2.1 power control circuit as the circuit system is involved in a variety of analog and digital parts of the operation of the chip, A / D sampling chip and FPGA chips are require two or more power supply, so select the appropriate voltage converter is very important. Power control circuit used Linear linear power supply module to provide A / D chip needs 3.3 V, 2.5 V voltage and FPGA required voltage of 3.3 V and 1.2 V in order to improve signal quality, analog and digital part of the 3.3 V supply by different power conversion modules.
2.2 data acquisition circuit data acquisition circuit is mainly composed by the AD7675 because the output I / O part of the 3.3 V supply, so all of its data output pin and input control signals are not the need for level conversion, directly with the FPGA I / O pins connected. A / D chip conversion rate 100KSPS, choose 16b bipolar complement output, the highest bit represents the sign bit. Hardware circuit shown in Figure 3. Collected data into the FPGA registers, then transmitted to a computer for data analysis.

AD7675 analog input part of the selection of AD AD8021 operational amplifier single-ended analog input signal differential signal conversion. Power supply pin before entering the nearest tantalum capacitors installed filter to reduce the clutter on the power supply, improve signal quality. AD7675 supports two kinds of parallel and serial data output mode, the system selects the parallel data output 16b complement of sampling, and related some of the control signals, such as BYTESWAP, OB, SER / PAR needs to be set to low. And RESET and other data output I / O pin access FPGA, the FPGA control.
2.3FPGA with the computer interface circuit
FPGA via a serial communication interface for communication with external computers. This selection of MAX232 to achieve LVTTL and EIA level conversion can be done easily between FPGA and computer RS232 communication.
2.4 digital temperature control unit design of the device software design is divided into two parts, one related to programming the FPGA, and its main features include: A / D data acquisition and control, serial data communication control, LCD read-write control and PROM burning, etc.; Second, computer-related program, the main features include numerical computation, calibration FPGA and storing the collected data for analysis. Throughout the FPGA design, developed by Altera Nios Ⅱ SoPC based processor and its software development kit can be easily SoPCBuilder required IP cores, memory, interface controllers, simple and fast integration into the FPGA to , thus shortening the design cycle. FPGA internal functional modules shown in Figure 4.

FPGA core control system is constituted by the 1400 ~ 1800LE, up and running can reach 86DMIPSD the f-type Nios Ⅱ CPU. In addition to CPU, the CNC system also includes a major sign system Nios Ⅱ system ID core; a JTAG serial asynchronous transceiver provides IP cores for FPGA-line debugging program; a standard can be achieved by any standard RS232 UART baud rate nucleus, the control circuit used in the successful commissioning work in stand-alone mode with an external computer communication; two sets of parallel input and output PIO core, respectively, the A / D sampling circuit to control and read A / D sampling data obtained; two an LCD controller IP core; a chip used to run the program ROM; a delivery system clock pll; an EPCS serial configuration device controller IP core. Figure 5.
system-generated schematic shown in Figure 6.

3 System Development Test System After the build, may need further testing to ensure its normal temperature. System development and testing process shown in Figure 7.

after the first observation on the power the major hardware is working properly, Nios Ⅱ IDE will generate the SOF file downloaded to the FPGA, Nios Ⅱ system to complete the download and initialization. Nios Ⅱ and then download the software through the JTAG port to the target system. System is working properly, the remote computer through the serial port on the A / D initialized data collection. Computer receives the A / D sampling data, can be calibrated for temperature control, data processing units to calculate the temperature of the device used to calibrate the calibration equation. Calibration process is as follows, the temperature control infrared receiver probes targeting heat, heat produces accurate temperature. In order to measure accurately, for the same temperature point, the use of multiple measurement averaging method. By the computer through the serial communication to record multiple A / D sample value and the corresponding temperature. Starting from low to high temperature, recorded by the computer through the serial communication under the A / D sample values. When the recorded values ??to reflect the temperature ranges can change the situation, you can let the computer used to generate the appropriate data fitting method to reflect the temperature is measured characteristic curve equations. Transmitted to the computer equation coefficients Nios Ⅱ system, complete the entire temperature measurement device calibration. Finally, check whether the FPGA Nios Ⅱ processor LCD controller and LCD through the normal communication, LCD can display normal character; Nios Ⅱ soft processors can achieve a normal read and write with PROM. After the success of commissioning in order to save resources, you can remove the JTAG debugger, and then the correct procedures in the burn to EPCS4. Then the program can be designed Nios Ⅱ IDE from the computer and run independently. Completed the entire development process temperature control can be used normally, the calibration temperature range of temperature measurement. Off-line measurements, generated by the timer on the A / D sampling clock pulses required, Nios Ⅱ system of two PIO, respectively, control the A / D control signal and the A / D sample value read into the Nios Ⅱ system. When in use, still use methods of averaging multiple measurements to get the A / D sample value, then the regression equation, the corresponding temperature can be obtained, then the system control Nios Ⅱ LCD controller R / W, RS and DB0 ~ DB7, the corresponding temperature value displayed on the LCD. When the need to use online, Nios Ⅱ system through the serial port will be stored in the internal A / D sampling values ??and the corresponding temperature values ??are sent to the computer to form a file for analysis.
4 Conclusion In this paper the design of digital circuits for temperature control of Altera Cyclone Ⅱ series FPGA as the core, from the completion of the overall program design to system commissioning and a series of processes. The total occupation of more than 3700 CNC LE, 99200 bit memory locations. For the entire temperature provides a stable and reliable data processing platform for higher-level extensions to provide a reference, have a very broad application prospects.